Title :
A comprehensive comparison of superior triple-threshold-voltage 7-transistor, 8-transistor, and 9-transistor SRAM cells
Author :
Hong Zhu ; Kursun, V.
Author_Institution :
Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China
Abstract :
Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing power supply voltage in scaled CMOS technologies. Triple-threshold-voltage seven-transistor (7T), eight-transistor (8T), and nine-transistor (9T) SRAM cells are characterized for layout area, data stability, write voltage margin, idle mode leakage currents, data access speed, and active power consumption considering process parameter fluctuations in a TSMC 65 nm CMOS technology in this paper. The single-ended and differential read / write schemes are also compared for data access speed and power consumption in SRAM circuits.
Keywords :
CMOS memory circuits; SRAM chips; 7T SRAM cells; 8T SRAM cells; 9T SRAM cells; SRAM circuits; TSMC 65 nm CMOS technology; differential read-write schemes; directly-accessed data storage nodes; eight-transistor SRAM cells; intrinsic data instability problem; nine-transistor SRAM cells; noise margins; process parameter fluctuations; read operation; scaled CMOS technologies; single-ended read-write schemes; size 65 nm; static random access memory cells; triple-threshold-voltage seven-transistor SRAM cells; Arrays; CMOS integrated circuits; CMOS technology; Circuit stability; Layout; SRAM cells; Memory integration density; data access speed; leakage current; noise immunity; power consumption; write voltage margin;
Conference_Titel :
Circuits and Systems (ISCAS), 2014 IEEE International Symposium on
Conference_Location :
Melbourne VIC
Print_ISBN :
978-1-4799-3431-7
DOI :
10.1109/ISCAS.2014.6865602
