Shift register multi-phase clock based downsampled floating tap DFE for serial links

This paper proposes a power/area efficient method for realizing a class of downsampled floating tap decision feedback equalization (DFE) architectures for serial links. The architectures offer significant complexity and power reduction over a standard floating tap DFE architecture with minimal performance loss. A shift register multi-phase clock based design in 28 nm CMOS is implemented for operation at 28.05 Gb/s. At 28.05 Gb/s, the designed downsampled architecture dissipates only 67% of the power of the corresponding standard architecture operating at 17 Gb/s. At the lower 17 Gb/s speed, the downsampled architecture dissipates only 45% of the power of the standard architecture.