DocumentCode
1769728
Title
Device Simulation of P-InAlN-Gate AlGaN/GaN high electron mobility transistor
Author
Shrestha, Niraj Man ; Yueh-Chin Lin ; Han-Tung Chang ; Yiming Li ; Chang, Edward Yi
Author_Institution
Dept. of Mater. Sci. & Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2014
fDate
3-6 June 2014
Firstpage
1
Lastpage
4
Abstract
Enhancement mode AlGaN/GaN high electron mobility transistor with p-InAlN gate is designed and successfully studied its electrical properties. Threshold voltage of the device is 1.9 V, which is required magnitude of threshold voltage for real device. Similarly, the maximum drain current is 520 mA/mm and trasconductance is 183 mS/mm, which is the record estimation for enhancement-mode (e-mode) device with recorded threshold voltage. P-InAlN layer injects hole to the barrier at higher gate voltage and results in comparatively larger drain current. Selective area etching and re-grow AlInN causes thin barrier layer beneath the gate. This recess like p-InAlN structure can reduce the concentration of 2DEG; and thus results the high magnitude of threshold voltage.
Keywords
III-V semiconductors; aluminium compounds; etching; gallium compounds; high electron mobility transistors; indium compounds; wide band gap semiconductors; 2DEG concentration; InAlN-AlGaN-GaN; device simulation; drain current; e-mode device; electrical properties; enhancement mode high electron mobility transistor; p-gate high electron mobility transistor; selective area etching; thin barrier layer; threshold voltage; voltage 1.9 V; Aluminum gallium nitride; Gallium nitride; HEMTs; Logic gates; MODFETs; Materials; Threshold voltage; 2 dimensional electron gas; Device simulation; Enhancement mode; High electron mobility transistor; Threshold voltage; p-AlInN;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Electronics (IWCE), 2014 International Workshop on
Conference_Location
Paris
Type
conf
DOI
10.1109/IWCE.2014.6865876
Filename
6865876
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