Title :
A high speed programmable frequency divider
Author :
Ping Jiang ; Ming Cheng ; Shengjun Lu ; Jinshun Lin
Author_Institution :
No.36 Res. Inst., CETC, Jiaxing, China
Abstract :
The design of a programmable frequency divider based on a pulse swallow counter is presented to meet the requirement of high speed working. An improved and optimized dual-modulus prescaler which is the core of the divider is proposed for trade-off between high speed and low power. The divider is fabricated in SMIC 0.18μm CMOS process, and the calculation and simulation results indicate its minimum division ratio is 307 while the maximum one is 1074. Simulations with Candence Spectre show the divider can operate upto 5GHz and the total current is only 1.94mA at the highest operation frequency and 308 division ratio.
Keywords :
CMOS integrated circuits; frequency dividers; prescalers; programmable circuits; Candence spectre; SMIC CMOS process; dual-modulus prescaler; high speed programmable frequency divider; pulse swallow counter; size 0.18 mum; CMOS integrated circuits; Frequency conversion; Frequency synthesizers; Phase locked loops; Radiation detectors; Simulation; Solid state circuits; high speed; prescaler; programmable frequency divider;
Conference_Titel :
Antennas and Propagation (APCAP), 2014 3rd Asia-Pacific Conference on
Conference_Location :
Harbin
Print_ISBN :
978-1-4799-4355-5
DOI :
10.1109/APCAP.2014.6992711
