FPGA interconnect modeling for lifetime failure detection

As FPGAs move into nanometer regime CMOS technology, new performance and lifetime limitations have started showing up. The process variation effects cause undesired behavior of the circuit as transistor dimensions decrease. This work makes an effort to understand the importance of routing in FPGAs and its impact on the performance of nanometer scale FPGAs. Lifetime failure of FPGAs can be detected by observing the variation in the delay performance from newly developed or developing faults. In this paper, we develop models of interconnect and switching networks that enhance delay estimation. Circuit simulations performed using these models are compared with the timing simulation results from Xilinx development tools.