Title :
Implementation of non-volatile 4×4 4T1D DRAM cell in 0.18μm technology
Author :
Joseph, Teena Susan ; Ravindran, Ajith
Author_Institution :
VLSI & Embedded Syst., Saintgits Coll. of Eng., Kottayam, India
Abstract :
This paper deals with the design and evolution of different 4×4 bit DRAM cells. Performances of different volatile 4×4 DRAM cells are compared. The comparison is done on the basis of power, area and delay. The 4×4 Non-Volatile (NVDRAM 4T1D) cell is proposed. The performance of the NVDRAM is then examined. The schematic entry was done using Mentor Graphics Design architect and simulations are done using Mentor Graphics Eldo. The simulation results obtained with TSMC 0.18μm process technology at 1.8V.
Keywords :
DRAM chips; electronic engineering computing; integrated circuit design; Mentor Graphics Design architect; Mentor Graphics Eldo; NVDRAM 4T1D cell; TSMC process technology; nonvolatile 4T1D DRAM cell; size 0.18 mum; word length 16 bit; Capacitors; Computer architecture; Graphics; Microprocessors; Nonvolatile memory; Random access memory; Transistors; 4×4 DRAM non-volatile operation; 4×4 DRAM volatile operation; Memory design;
Conference_Titel :
Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014 International Conference on
Conference_Location :
Kanyakumari
Print_ISBN :
978-1-4799-4191-9
DOI :
10.1109/ICCICCT.2014.6993001
