Clock jitter in sampling and reconstruction

Clock jitter plays an important role in A/D and D/A conversions. Various aspects of this problem have been extensively studied. We consider here the effect of clock jitters in the basic system of digital filtering of analog signals. The system consists of an A/D, followed by a digital filter, and then followed by a hold circuit for D/A reconstruction. Thus the readout jitter affects both the leading edge and the trailing edge of the rectangular pulse in the reconstruction. This system includes the familiar sampling of an analog signal and subsequent reconstruction from its samples. Expressions are derived for the mean squared error caused by the sampling clock jitter and readout clock jitters. Expressions are also derived showing how the signal spectra are modified by clock jitters.