A Wideband 6.9–17.7 GHz CMOS low-noise amplifier with a gain flattening technique

A flat-gain design of an ultra wide-band CMOS amplifier is proposed and simulated in 90 nm CMOS process. Inductive degeneration is applied to reduce noise figure without significantly raising the architecture´s power requirement. Additionally, a resistive shunt feedback technique is applied with an RL peaking load to flatten the gain throughout design band. This topology allows the amplifier to have a very large bandwidth of 6.9-17.7 GHz with a low minimum noise figure of 2.26 dB (at 10 GHz). NF also remains below 5.2 dB across the 10.8 GHz bandwidth. The design exhibits gain which peaks to 11.1 dB and has a low power demand of 15.7 mW (from a 1.2 V supply). Comparing the circuit performance to previously published amplifiers shows that it achieves reduction in NF and power dissipation while maintaining a flatter gain in X-K band.