Fully integrated CMOS doherty power amplifier with network matching optimization for die size reduction

Author

Carneiro, Marcos L. ; Deltimple, Nathalie ; Carvalho, Paulo H. P. ; Belot, Didier ; Kerherve, Eric

Author_Institution

Electr. Eng. Dept., Univ. of Brasilia, Brasilia, Brazil

fYear

2014

fDate

6-7 Oct. 2014

Firstpage

325

Lastpage

328

Abstract

Impedance network topology optimization method is proposed for saving die area and increasing performance. The technique was applied on a fully integrated Doherty Power Amplifier design in 65nm CMOS technology. Measurement results achieve a constant 24% PAE performance over a 7 dB backoff, P_out of 23.4dBm and 15dB of gain. The optimization allowed the reduction of the number of inductors which reduced in 59% the expected die area and also increased the PAE mean performance in 5% on the high power stage and the P_out in 2dB.

Keywords

CMOS integrated circuits; integrated circuit design; network topology; optimisation; power amplifiers; CMOS technology; die size reduction; fully integrated CMOS doherty power amplifier; gain 15 dB; impedance network topology optimization method; network matching optimization; size 65 nm; CMOS integrated circuits; CMOS technology; Capacitors; Frequency measurement; Inductors; Optimization; Power amplifiers; CMOS integrated circuit; circuit optimization; design methodology; power amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

European Microwave Integrated Circuit Conference (EuMIC), 2014 9th

Conference_Location

Rome

Type

conf

DOI

10.1109/EuMIC.2014.6997858

Filename

6997858