SiC graphene FET with polydimethylglutharimide as a gate dielectric layer

Graphene is perspective material for future carbon based electronics, flexible electronics and other applications. The necessary condition for the commercial use is the high quality graphene growth and semiconductor technology compatible process of whole field effect transistor (FET). One of suitable method for large scale graphene monolayer preparation is the thermal annealing of semi-insulating SiC substrate. One important task of graphene FET process is reliable, cheap and simple gate structure preparation. In this work we present our results of using MicroChem Lift-Off Resist (LOR) layer as a dielectric layer for SiC graphene FETs. LOR resist is based on polydimethylglutharimide. Its unique properties enable to perform exceptionally well resolution imaging, easy process tuning, high yields and superior deposition line width control. In the case of polymer based dielectric layers the breakdown voltage is important parameter. We prepared two sets of different capacitor structures with LOR dielectric layer and Au/Cr electrodes. The first set exhibits very low breakdown voltages (about 3 V). The optimisation of the LOR layer deposition process in the second set increased the breakdown voltage over 40 V keeping the leakage current lower than 2 nA. The second process with LOR layer was used for the preparation of graphene FETs on SiC substrates. The first measurements show resistivity dependence on gate voltage.