Design and simulation of low-power and high speed T-Flip Flap with the modified gate diffusion input (GDI) technique in nano process

The basic element in designing the circuit function single-flux quantum (SFQ) like demultiplexer, frequency dividers and binary counters in integrated circuits is Toggle flip flop (TFF). By using gate diffusion input (GDI) technique in designing the logic gates, power consumption, delay, chip area and connection and parasitic capacitors are decreased. In this paper, first, the modified GDI (m-GDI) cell is proposed, based on the basic GDI cell, then the master-slave Data flip flap (DFF) with employing m-GDI cell is presented. With the help of the proposed DFF and combinational logic function of the proposed m-GDI cell, the master-slave TFF which works at high frequency is designed. As a result of using one phase clock in designing the proposed TFF, the complexity of adjusting the speed in complementary clock signals is significantly improved in comparison with the conventional flip flops. The simulation results show that the essential criteria for evaluating flip flops like power delay product (PDP) and energy delay product (EDP) is improved about 63% and 85%, respectively. Also the chip area of the proposed flip flap is basically ameliorated in comparison with the TFF using basic GDI cell and the other flip flops that hve been designed with the conventional techniques. The simulation is done with H-SPICE software in 32nm technology under the condition of 0.9V supply voltage, 500MHz frequency and room temperature.