On the stability of integer-N phase locked loops based on a straightforward design methodology

The closed loop structure of ring-oscillator based integer-N PLLs, to achieve a desired phase margin, is thoroughly analyzed. Furthermore, a straightforward design methodology is implicitly introduced. The analysis proves that the ratio of the large capacitance to the small one, for a 65 degrees phase margin, in the loop filter of integer-N PLLs, should be at least 20 rather than 7 to 10, which is commonly practiced based on some widely read literatures, [6]. There are works, however, which have used greater capacitance ratios, 13, 20 and 32, without providing a theoretical base. Also, enhancing phase margin to 70 and 80 degrees requires capacitance ratios of 31 and 130, respectively. It is also proved that the maximum phase margin is achieved when the unity gain bandwidth, ω_u, is adjusted at the geometrical median frequency of the zero and the third pole. Simulation results confirm 35% and 50% improvement in RMS and peak to peak jitter at 250MHz operating frequency, respectively, when the ratio of capacitances is modified from 10 to 20.