An analytical dynamic and leakage power model for FPGAs

Managing power by means of architectural optimization has emerged as one of the most important FPGA-based design challenges. In this paper, we present an analytical model to estimate the dynamic and leakage power for a wide variety of FPGA architectures. The proposed power model has been integrated into the Geometric Programming framework in order to investigate the impact of various architectural parameters on the power-efficiency of FPGAs. This way, we are able to rapidly analyze various FPGA architectures and select the best one in terms of a combination of dynamic and static power consumptions. The results show that up to 9X run time improvement in comparison with VPR based power analysis is achieved. Our method also shows that the optimal values for LUT-size and cluster-size are 5 and 8-10, respectively.