Title :
UVM based STBUS verification IP for verifying SoC architectures
Author :
Samanta, Pranay ; Chauhan, Deepak ; Deb, Sujay ; Gupta, Pragya Kirti
Author_Institution :
Indraprastha Inst. of Inf. Technol. New Delhi, Electron. & Commun. Eng., New Dehli, India
Abstract :
In this paper, we propose the design and development of verification IP (VIP) of STBUS, a widely used bus protocol from STMicroelectronics [1]. VIP is a standalone, pre-verified and built-in verification infrastructure, which can be easily plugged in the simulation-based tests. We have followed Universal Verification Methodology (UVM) for the modelling of the STBUS VIP. Firstly we have verified the important properties of the STBUS protocol and made the VIP. Then we have shown how to use the VIP in a SoC to verify IPs.
Keywords :
integrated circuit design; microprocessor chips; protocols; system-on-chip; STBUS protocol; STMicroelectronics; SoC architectures; UVM based STBUS verification IP; VIP; built-in verification infrastructure; bus protocol; simulation-based tests; universal verification methodology; IP networks; Information technology; Microelectronics; Monitoring; Protocols; Registers; System-on-chip; DUT; STBUS; UVM; VIP; functional verification;
Conference_Titel :
VLSI Design and Test, 18th International Symposium on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-5088-1
DOI :
10.1109/ISVDAT.2014.6881037
