DocumentCode
1787016
Title
Enabling dynamic heterogeneity through core-on-core stacking
Author
Kontorinis, Vasileios ; Tavana, Mohammad K. ; Hajkazemi, Mohammad H. ; Tullsen, Dean M. ; Homayoun, Houman
Author_Institution
Google, Venice Beach, CA, USA
fYear
2014
fDate
1-5 June 2014
Firstpage
1
Lastpage
6
Abstract
Future computing platforms will need to be flexible, scalable, and power-conservative, while saving size, weight, energy, etc. Heterogeneous architecture can address these challenges by allowing each application to run on a core that matches resource needs more closely than a one-size-fits-all core. Dynamic heterogeneous architectures can extend these benefits further, allowing the system to construct the right core at run-time for each application, borrowing or freeing resources only as needed by the particular application that is running. The key insight in the described design is that 3D stacking of cores eliminates the fundamental barrier to dynamic heterogeneity, allowing various resources belonging to different cores to be shared at run-time with minimal overhead.
Keywords
integrated circuit design; microprocessor chips; three-dimensional integrated circuits; 3D stacking; core-on-core stacking; dynamic heterogeneity; dynamic heterogeneous architectures; Multicore processing; Pipelines; Registers; Resource management; Stacking; Three-dimensional displays; 3D stacking technology; core-on-core stacking; energy efficiency; resource pooling;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE
Conference_Location
San Francisco, CA
Type
conf
Filename
6881509
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