Synthesis of locally-clocked asynchronous systems with bundled-data implementation on FPGAs

This paper presents a method for an optimized synthesis of asynchronous digital systems having an FPGA as target device. The method employs the decomposition design style (data-path + controller) and uses the extended burst-mode specification to describe the controller. Asynchronous system synthesized by the method operates in “two-phase handshake protocol”, allowing a better performance. In this method, the decomposition is implemented by bundled-data using components of the synchronous paradigm. This new method proposes to design asynchronous FSM with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any programmable device, such as CPLDs and FPGAs, without macro-cells´ mapping concern A with four benchmarks shows an average performance increase of 21% with an average area increase of 27% LUTs, when compared with synchronous versions.