Glitch elimination and optimization of dynamic power dissipation in combinational circuits

Low power consumption has become a highly important concern for the designs. Glitches contribute to the dynamic power which itself is a major portion of the total power consumed by designs. A glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits due to differential delay at the inputs of a gate. The paper describes a procedure to estimate and optimize dynamic power dissipation for combinational circuits due to propagation delay. First, cause of glitch and power dissipated due to presence of it is estimated. Secondly, a technique using transmission gate is employed and the glitch is eliminated. Then a comparison of the power dissipated is carried out to know the optimized power for 1.2μm and 0.8μm CMOS Technologies.