Design of a power efficient SPI interface

This paper is about the design of an SPI interface which is based on the specifications mentioned in the SPI block guide V03.06 by Motorola. The present design includes an additional power down mode-stop mode for power optimization and the standard design has been modified by the technique of clock gating for additional power reduction. The shifter module of the interface has been designed with double buffered registers to prevent the loss of data due to overflow. By using clock gating in the design the power has been reduced from 28.2% (min) to 31.5% (max). The coding has been done using Verilog and the simulated results have been observed in I-Sim (Xilinx).