An algorithmic approach for leakage current reduction in deep sub-micron CMOS circuits

There are several techniques available to control the leakage current in deep sub-micron technologies. One of the techniques is the Input Vector Control (IVC). By using IVC, leakage power consumption of a circuit can be minimized in the off state. In this paper, an algorithm has been given to calculate the best input vector that can be applied to the circuit (designed with 65nm technology transistors) in the off state for obtaining the low leakage current. The concept of controllability of the nodes in the circuit and the inter dependency of the gates in the circuit were used to determine the best input vector in the algorithm. Exclusive OR gate with NAND gates is used to test the algorithm, the results showed that the algorithm gives an input vector that can be applied to the circuit in the sleep state which is same as that of the vector obtained using an exhaustive search in CADENCE SPECTRE, with less computational time.