Wafer-level packaging for harsh environment application

Author

Jia, Chungang ; Bardong, J. ; Gruber, Christoph ; Kenda, A. ; Kraft, Michael

Author_Institution

CTR Carinthian Tech Res. AG, Villach, Austria

fYear

2014

fDate

15-16 July 2014

Firstpage

39

Lastpage

39

Abstract

A wafer-level chip-scale packaging scheme that can withstand temperatures of 600°C and above in long-term operation is proposed. The package comprises a SOI case and a cap wafer. In the device layer of the SOI wafer, flexible springs are formed to fix target chips inside the case, so that the influence of thermal stress can be minimized. The two components are joined together through wafer bonding process under vacuum condition. Electric connection is established through Pt metallized via in SOI. Initial test results confirm the feasibility of the method.

Keywords

chip scale packaging; integrated circuit interconnections; platinum; silicon-on-insulator; thermal stresses; three-dimensional integrated circuits; wafer bonding; wafer level packaging; Pt; SOI wafer; electric connection; flexible springs; harsh environment application; temperature 600 degC; thermal stress; wafer bonding process; wafer-level chip-scale packaging; Cavity resonators; Metals; Packaging; Plasma temperature; Silicon-on-insulator; Stress; Temperature sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Temperature Bonding for 3D Integration (LTB-3D), 2014 4th IEEE International Workshop on

Conference_Location

Tokyo

Print_ISBN

978-1-4799-5260-1

Type

conf

DOI

10.1109/LTB-3D.2014.6886178

Filename

6886178