A low power baseband processor for a dual mode UHF EPC Gen 2 RFID tag

Author

Roostaie, Vahid ; Najafi, Vali ; Mohammadi, Siamak ; Fotowat-Ahmady, Ali

Author_Institution

Unistar Micro Technol. Inc., Richmond Hill, ON

fYear

2008

fDate

25-27 March 2008

Firstpage

1

Lastpage

5

Abstract

In this paper, the digital core of a low power RFID chip based on the EPC Gen 2 protocol is presented. EPC class 1 generation 2 is the most acceptable and comprehensive passive RFID protocol today. The novel dual mode architecture enables the chip to work in passive and battery-assisted modes controlled by reader. Several low power techniques are employed to reduce the power consumption of the chip which is essential in passive RFID tags. The chip has been designed and fabricated in standard 0.18um CMOS process. Power analysis shows that the digital core consumes 6.4 muW at IV supply voltage when it comcates wih the reader.

Keywords

CMOS integrated circuits; low-power electronics; power consumption; protocols; radiofrequency identification; CMOS; EPC Gen 2 protocol; RFID; low power baseband processor; power consumption; Baseband; Batteries; Energy consumption; Passive RFID tags; Protocols; RFID tags; Radio frequency; Radiofrequency identification; Switches; Transponders; EPC Gen 2; RFID; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Technology of Integrated Systems in Nanoscale Era, 2008. DTIS 2008. 3rd International Conference on

Conference_Location

Tozeur

Print_ISBN

978-1-4244-1576-2

Electronic_ISBN

978-1-4244-1577-9

Type

conf

DOI

10.1109/DTIS.2008.4540230

Filename

4540230