Yield-driven minimum energy CMOS cell design

CMOS circuits operating near or below threshold offer the lowest energy per computation. Previous work reduces the total energy by using minimum sizing and lowering the voltage without concern for yield. To achieve better yield, the voltage or size must increase. The minimum energy point for minimum-sized NAND2 gates in a 65 nm process is 0.475 V consuming 0.0275 fJ/cycle with a gate failure rate of 2×10^-4. However, to achieve a failure rate of 10^-6, minimum energy is achieved by widening pMOS transistors by 50%, increasing total energy by 11.9%, which is 7.2% better than minimum width devices and higher voltage.