Sparse polynomial equalization of an RF receiver via algorithm, analog, and digital codesign

Nonlinear circuit behavior degrades system performance of RF receivers operating near the compression point, causing both in-band and out-of-band distortions. Linearity can be improved through analog design changes at the cost of greater power consumption. Alternatively, digital compensation algorithms can alleviate nonlinear distortions, but standard combinatorial models of nonlinear system behavior can require high-power digital circuits. We present preliminary results of a co-optimized receiver and digital equalizer achieving 80 dB spurious free dynamic range over 49 MHz while dissipating 132 mW. We describe the codesign process used to optimize power consumption across analog and digital circuits while meeting high linearity requirements.