Efficient hardware architecture of recursive Karatsuba-Ofman multiplier

The finite Field multiplication is the basic operation in all cryptographic applications. It can be performed by using Serial, Booth, Montgomery and Karatsuba-Ofman´s divide-and-conquer technique. The Karatsuba-Ofman multiplier replaces a multiplication by three ones of half-length operands which are performed in parallel. The implementation of Karatsuba-Ofman multiplier has been made both in sequential and parallel architectures. In order to improve the performance´s architectures over GF (2m), we propose a new Sequential/Parallel architectures of Recursive Karatsuba-Ofman multiplier. In this paper, two Sequential/Parallel architectures are presented, developed and implemented on the Spartan 3 FPGA platform. Area and low Delay computation of the proposed architectures are improved. Mathematical Performances models (Area (n), Delay (n)) for large number (n) are elaborated for our proposed architectures. They can be established in order to expect the appropriate multiplier for the cryptographic applications.