Title :
An Optimized Design of MCU in CPU Soft-core Based on the FPGA
Author :
Yuhua, Xing ; Ru, Wang
Author_Institution :
Xi´´an Univ. of Tech., Xi´´an
fDate :
Aug. 16 2007-July 18 2007
Abstract :
Through the discussion of the structure and the design process about micro-programmed control unit (MCU) in CPU soft-core. An optimized design method of next-address shift logic in MCU is presented in this paper by designing instruction operating code and arranging microinstructions storage. Some of codes using Verilog HDL are given. Simulation result indicate that this method is practical and has reference value in designing CPU soft-core based on the FPGA.
Keywords :
field programmable gate arrays; hardware description languages; logic circuits; microcontrollers; CPU soft-core; FPGA; Verilog HDL; instruction operating code; micro-programmed control unit; microinstructions storage; next-address shift logic; optimized MCU design; Control systems; Data communication; Design optimization; Field programmable gate arrays; Hardware design languages; Instruments; Logic design; Microprocessors; Process control; Process design; FPGA; MCU; Verilog_HDL; address shift logic;
Conference_Titel :
Electronic Measurement and Instruments, 2007. ICEMI '07. 8th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4244-1136-8
Electronic_ISBN :
978-1-4244-1136-8
DOI :
10.1109/ICEMI.2007.4351301
