DocumentCode :
1803029
Title :
Learning for evolutionary design
Author :
Louis, Sushil J.
Author_Institution :
Dept. of Comput. Sci., Univ. of Nevada, Reno, NV, USA
fYear :
2003
fDate :
9-11 July 2003
Firstpage :
17
Lastpage :
20
Abstract :
This paper describes a technique for evolving similar solutions to similar configuration design problems. Using the configuration design of combination logic circuits as a test bed, the paper shows that combining genetic algorithms with a case-based memory leads to improved performance on sets of similar design problems. In this approach, rather than starting from scratch on each design, we periodically inject a genetic algorithm´s population with appropriate partial solutions to similar previously attempted problems. Experimental results on the combinational logic design of parity checkers and adders shows that this system takes less time to provide better quality solutions to new design problems as it gains experience from solving other similar design problems. The designs generated by the combined system also tend to be more similar than those generated by a randomly initialized genetic algorithm. This implies that the system can be used for quick, high quality re-design so that when components fail or deteriorate, we can quickly regain lost or deteriorating functionality.
Keywords :
case-based reasoning; circuit CAD; genetic algorithms; integrated circuit design; learning (artificial intelligence); parallel algorithms; reconfigurable architectures; CIGAR; case injected genetic algorithm; case-based reasoning; combination logic circuit; combinational logic design; combined system; component deterioration; component failure; configuration design problem; evolutionary design; high quality redesign; machine learning system; parity adder; parity checker; partial solution; performance gain; randomized parallel search algorithm; randomly initialized genetic algorithm; Adders; Algorithm design and analysis; Circuit testing; Computer science; Genetic algorithms; Hardware; Laboratories; Logic circuits; Logic design; Logic testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Evolvable Hardware, 2003. Proceedings. NASA/DoD Conference on
Print_ISBN :
0-7695-1977-6
Type :
conf
DOI :
10.1109/EH.2003.1217637
Filename :
1217637
Link To Document :
بازگشت