DocumentCode :
1803511
Title :
Hardware spiking neural network with run-time reconfigurable connectivity in an autonomous robot
Author :
Roggen, Daniel ; Hofmann, Stéphane ; Thoma, Yann ; Floreano, Dario
Author_Institution :
Inst. of Syst. Eng., Autonomous Syst. Lab., Lausanne, Switzerland
fYear :
2003
fDate :
9-11 July 2003
Firstpage :
189
Lastpage :
198
Abstract :
A cellular hardware implementation of a spiking neural network with run-time reconfigurable connectivity is presented. It is implemented on a compact custom FPGA board, which provides a powerful reconfigurable hardware platform for hardware and software design. Complementing the system, a CPU synthesized on the FPGA takes care of interfacing the network with the external world. The FPGA board and the hardware network are demonstrated in the form of a controller embedded on the Khepera robot for a task of obstacle avoidance. Finally, future implementations on new multi-cellular hardware are discussed.
Keywords :
cellular neural nets; field programmable gate arrays; hardware-software codesign; mobile robots; neurocontrollers; reconfigurable architectures; FPGA board; Khepera robot; autonomous robot; cellular spiking neural network; controller embedding; field programmable gate array; hardware design; network interfacing; obstacle avoidance; powerful reconfigurable hardware platform; run-time reconfigurable connectivity; software design; Cellular networks; Cellular neural networks; Control system synthesis; Field programmable gate arrays; Network synthesis; Neural network hardware; Neural networks; Robots; Runtime; Software design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Evolvable Hardware, 2003. Proceedings. NASA/DoD Conference on
Print_ISBN :
0-7695-1977-6
Type :
conf
DOI :
10.1109/EH.2003.1217666
Filename :
1217666
Link To Document :
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