A reduced multistage architecture for ATM networks

Author

Syed, M. ; Ilyas, M.

Author_Institution

Dept. of Comput. Eng. & Sci., Florida Atlantic Univ., Boca Raton, FL, USA

fYear

1991

fDate

23-26 Jun 1991

Firstpage

369

Abstract

A novel communication switch architecture for ATM (asynchronous transfer mode) networks is presented. The speed of the proposed switch architecture is clock-rate-dependent. This architecture has a modular structure and provides a pipeline activity which reduces head-of-line blocking. As a result of using this architecture, the number of stages required is one half the number of stages used in switches today. This results in a reduction of delay to a maximum of 100% for the ideal case and to 20% on average and a reduction in throughput delay of 25% for the nonideal case when compared with a Banyan network. Because of its high degree of modularity, the architecture can be easily implemented using VLSI techniques

Keywords

ISDN; broadband networks; electronic switching systems; time division multiplexing; ATM networks; B-ISDN; Banyan network; asynchronous transfer mode; clock-rate-dependent; communication switch architecture; delay reduction; head-of-line blocking; modular structure; pipeline activity; reduced multistage architecture; throughput delay; Application software; Asynchronous transfer mode; B-ISDN; Communication switching; Computer architecture; Packet switching; Protocols; Switches; Telecommunication traffic; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 1991. ICC '91, Conference Record. IEEE International Conference on

Conference_Location

Denver, CO

Print_ISBN

0-7803-0006-8

Type

conf

DOI

10.1109/ICC.1991.162392

Filename

162392