DocumentCode :
1806401
Title :
Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System
Author :
Kinsy, Michel A. ; Pellauer, Michael ; Devadas, Srinivas
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
fYear :
2011
fDate :
5-7 Sept. 2011
Firstpage :
356
Lastpage :
362
Abstract :
Heracles is an open-source complete multicore system written in Verilog. It is fully parameterized and can be reconfigured and synthesized into different topologies and sizes. Each processing node has a fully bypassed, 7-stage pipelined microprocessor running the MIPS-III ISA, a 4-stage input-buffer, virtual-channel router, and a local variable-size shared memory. Our design is highly modular with clear interfaces between the core, the memory hierarchy, and the on-chip network. In the baseline design, the microprocessor is attached to two caches, one instruction cache and one data cache, which are oblivious to the global memory organization. The memory system in Heracles can be configured as one single global shared memory (SM), or distributed shared memory (DSM), or any combination thereof. Each core is connected to the rest of the network of processors by a parameterized, realistic, wormhole router. We show different topology configurations of the system, and their synthesis results on the Xilinx Virtex-5 LX330T FPGA board. We also provide a small MIPS cross-compiler tool chain to assist in developing software for Heracles.
Keywords :
cache storage; distributed shared memory systems; field programmable gate arrays; hardware description languages; network routing; network topology; 4-stage input-buffer; Heracles; MIPS cross-compiler tool chain; MIPS-III ISA; Verilog; Xilinx Virtex-5 LX330T FPGA board; data cache; distributed shared memory; fully synthesizable parameterized MIPS-based multicore system; global memory organization; global shared memory; instruction cache; local variable-size shared memory; memory hierarchy; memory system; on-chip network; open-source complete multicore system; pipelined microprocessor; topology configurations; virtual-channel router; wormhole router; Field programmable gate arrays; Multicore processing; Network topology; Random access memory; Routing; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2011 International Conference on
Conference_Location :
Chania
Print_ISBN :
978-1-4577-1484-9
Electronic_ISBN :
978-0-7695-4529-5
Type :
conf
DOI :
10.1109/FPL.2011.70
Filename :
6044843
Link To Document :
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