DocumentCode
1806548
Title
A non-feedback multiphase clock generator
Author
Yang, Lixin ; Zhou, Yijun ; Yuan, Jiren
Author_Institution
Dept. of Electroscience, Lund Univ., Sweden
Volume
4
fYear
2002
fDate
2002
Abstract
This paper introduces the design of a new multiphase clock generator with no feedback loop. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1.5 GHz.
Keywords
CMOS analogue integrated circuits; UHF integrated circuits; frequency dividers; interpolation; signal generators; 0.35 micron; 1/4 frequency divider; 3.3 V; 500 MHz to 1.5 GHz; CMOS process; input clock frequency range; multiphase clock generator; no feedback loop; short-circuit current suppression interpolator; single-stage direct interpolation architecture; CMOS technology; Circuits; Clocks; Feedback loop; Frequency; Interpolation; Inverters; Phase locked loops; Signal generators; Signal resolution;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1010473
Filename
1010473
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