Title :
Design trade-offs of a symmetric linearized CMOS LC VCO
Author :
Dülger, Fikret ; Sánchez-Sinencio, Edgar
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
Trade-offs in a CMOS LC symmetric VCO design with spiral inductors and bulk-tuned PMOS capacitors are presented. Source-degeneration resistors used to linearize the negative resistance generator provide additional design degrees of freedom, trading the close-in phase noise with the phase noise at large offsets. Measured tuning range around 2.15 GHz is 3.5% due to the limitation of the well resistance of the bulk-tuned capacitors. Spiral inductors with Q of 2.5 at 2 GHz limit the phase noise to -126 dBc/Hz at 3 MHz offset from a 2.19 GHz carrier. The VCO implemented in a 0.5 μm CMOS technology consumes 4 mA from a 3 V supply.
Keywords :
CMOS analogue integrated circuits; UHF integrated circuits; UHF oscillators; capacitors; circuit tuning; inductors; integrated circuit design; integrated circuit noise; linearisation techniques; phase noise; voltage-controlled oscillators; 0.5 micron; 2.15 GHz; 2.19 GHz; 3 V; 4 mA; CMOS LC symmetric VCO design; bulk-tuned PMOS capacitors; bulk-tuned capacitor well resistance; design degrees of freedom; design trade-offs; negative resistance generator linearization; phase noise; source-degeneration resistors; spiral inductors; symmetric linearized CMOS LC VCO; tuning range; CMOS technology; Capacitors; Circuits; Electrical resistance measurement; Inductors; MOSFETs; Phase noise; Radio frequency; Resistors; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010475
