Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays

This paper presents several novel low-power low-distortion ΔΣ modulator topologies with shifted loop delays. Both single-sampled and double-sampled modulators are discussed. The proposed architectures can relax the critical timing for quantization and for dynamic element matching. A delay-free integrator in the last stage is used to perform the active summation, hence eliminating the active adder. The reduced input swing of the last integrator relaxes the OTA´s requirements. The proposed topology simplifies the feed-forward paths, and saves power consumption and capacitor area. Noise-coupled technique can also be utilized to enhance the noise shaping. To verify the effect of the proposed topology, single- and double-sampled third-order ΔΣ modulators with and without noise coupling were analyzed and simulated.