A 0.47–1.6mW 5bit 0.5–1GS/s time-interleaved SAR ADC for low-power UWB radios

Author

Harpe, Pieter ; Busze, Ben ; Philips, Kathleen ; De Groot, Harmke

Author_Institution

Holst Centre, Imec, Eindhoven, Netherlands

fYear

2011

fDate

12-16 Sept. 2011

Firstpage

147

Lastpage

150

Abstract

This paper presents a 16-channel time-interleaved 5-bit asynchronous SAR ADC for UWB radios. It proposes 400aF unit capacitors, offset calibration, a self-resetting comparator and a distributed clock divider to optimize the performance. The prototype in 90nm CMOS occupies only 0.11mm² including decoupling capacitors. Two relevant modes for UWB are supported: 0.5GS/s at 0.75V supply, and 1GS/s at 1V supply with 0.47mW and 1.6mW power consumption respectively. With an ENOB of 4.7 and 4.8bit, this leads to energy efficiencies of 36 and 57fJ/conversion-step. Compared to prior-art, state-of-the-art efficiency is achieved without relying on complex calibration schemes.

Keywords

CMOS integrated circuits; analogue-digital conversion; capacitors; clocks; comparators (circuits); low-power electronics; ultra wideband communication; CMOS integrated circuit; asynchronous SAR ADC; capacitance 400 nF; decoupling capacitors; distributed clock divider; low-power UWB radios; offset calibration; power 0.47 mW to 1.6 mW; self-resetting comparator; size 90 nm; time-interleaved SAR ADC; voltage 0.75 V; voltage 1 V; Accuracy; CMOS integrated circuits; Calibration; Capacitors; Clocks; Layout; Logic gates;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2011 Proceedings of the

Conference_Location

Helsinki

ISSN

1930-8833

Print_ISBN

978-1-4577-0703-2

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2011.6044886

Filename

6044886