A 5-stage pipelined embedded processor with optimized handling exception

This paper presents the design and implementation of a embedded processor, xCore_AHB, featuring precise interrupt and exception, which is compatible with ARMv4 architecture. The precise exception mechanism of this design provides not only the quick entrance of the interrupt handle programs but also the interrupt handle programs with the right return address by an additional program counter in write back stage of the pipeline and its support circuits. The proposed exception controller saves about 30% area compared with the traditional exception controller. The proposed design has been implemented with the 0.18um IP6M CMOS process of SMIC. The chip operates 1.2DMIPS at a frequency of 100MHz with 33mW power dissipation.