Modeling Semiconductor Tools for Small Lotsize Fab Simulations

Short cycle times are critical to the success of semiconductor manufacturing. The addition of more and more mask layers leads to higher raw process times and makes short cycle times an increasingly challenging task. One cycle time reduction possibility semiconductor manufacturers now look at is lotsize reduction. A reduction in lotsize transfers directly into lower raw process times. Modeling and simulation are key to assess opportunities and risks of such an approach. This paper looks at the implications that follow from small lotsizes for tool models used for the assessment