High performance parallel multiplier using Wallace-Booth algorithm

Author

Lakshmanan ; Othman, Masuri ; Ali, Mohamad Alauddin Mohd

Author_Institution

Dept. of Electr., Electron. & Syst. Eng., Univ. Kebangsaan Malaysia, Selangor, Malaysia

fYear

2002

fDate

19-21 Dec. 2002

Firstpage

433

Lastpage

436

Abstract

This paper presents an efficient implementation of a VLSI high speed parallel multiplier using the Radix_4 modified Booth algorithm and the Wallace Tree structure. The design is structured for a n×m multiplication where n can reach up to 126 bits. The Wallace Tree structure serves to compress the partial product term by a ratio of 3:2. To enhance the speed of operation, carry-look-ahead(CLA) adders are used which is independent on the number of bits of the two operands. An efficient VHDL code was written and successfully simulated and synthesised using Altera´s MaxplusII(10.0) and ModelSim3.4 CAD tools.

Keywords

VLSI; algorithm theory; hardware description languages; Radix_4 modified Booth algorithm; VHDL code; VLSI high speed parallel multiplier; Wallace Tree structure; Wallace-Booth algorithm; carry look ahead adders; Adders; Algorithm design and analysis; Design engineering; Digital signal processing chips; Logic arrays; Signal design; Signal processing algorithms; Systems engineering and theory; Tree data structures; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 2002. Proceedings. ICSE 2002. IEEE International Conference on

Print_ISBN

0-7803-7578-5

Type

conf

DOI

10.1109/SMELEC.2002.1217859

Filename

1217859