Keynote

Since yield is not 100%, the main objective of test has and continues to be screening out bad ICs. Today, however, test is being used to provide valuable information about failing chips, answering questions about whether the design, the fabrication process or some combination of the two is responsible for failure. The information extracted is, ideally, used to improve design, fabrication and even test itself. In this talk, an overview of research in the Carnegie Mellon Advanced Chip Testing Laboratory in this area will be described with particular emphasis on one methodology that focuses on measuring the effectiveness of any fault model or test metric using normally-available test data. Experiment results from manufactured chips from both IDMs and chip-design houses will be used to illustrate the potential of this approach.