DocumentCode
180902
Title
Testability-Driven Fault Sampling for Deterministic Test Coverage Estimation of Large Designs
Author
Kun-Han Tsai
Author_Institution
Mentor Graphics Corp., Wilsonville, OR, USA
fYear
2014
fDate
16-19 Nov. 2014
Firstpage
119
Lastpage
124
Abstract
The continuously increasing complexity and size of the modern high performance design often introduces the testability barriers which either restrict the desirable test quality, or require extended test generation time. To detect such testability barriers and accurately estimate the test coverage quickly is important to minimize the risk of test quality issue or any later stage design change. The paper proposes a novel technique to efficiently estimate the deterministic test coverage for large designs. The test coverage estimation with less than 0.5% error can be achieved with more than 30X run time reduction compared to the test generation run time of the entire fault population.
Keywords
automatic test pattern generation; fault diagnosis; integrated circuit design; integrated circuit testing; deterministic test coverage estimation; test generation time; testability driven fault sampling; Automatic test pattern generation; Circuit faults; Equations; Estimation; Logic gates; Mathematical model; Measurement; ATPG; test coverage estimation; testability measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ATS), 2014 IEEE 23rd Asian
Conference_Location
Hangzhou
ISSN
1081-7735
Type
conf
DOI
10.1109/ATS.2014.32
Filename
6979087
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