Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories

Fault scrambling technique is considered a promising way to distribute faulty bits into different code words such that the number of faulty cells in each codeword is below the protection capability of the adopted EDAC coding techniques. However, the effectiveness of the scrambling technique depends on the determination of the row/column scrambling control words. Therefore, we propose a heuristic algorithm suitable for built-in implementation for the evaluation of control words based on the fault bitmap and the specifications of the memory. The corresponding built-in scrambling analysis (BISA) circuit is also proposed. The BISA module can be easily integrated into the conventional built-in self-repair (BISR) module. A simulator is developed to evaluate the hardware overhead and repair rate. According to experimental results, the repair rate can be improved significantly with negligible hardware overhead.