Charge-based MOS correlated double sampling comparator and folding circuit

Author

Genov, Roman ; Cauwenberghs, Gert

Author_Institution

Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

Volume

5

fYear

2002

fDate

2002

Abstract

A novel charge-based comparator and folding circuit are presented. Correlated double sampling comparison is performed using a log-domain integrator, implemented by a subthreshold nMOS transistor with the source coupled to a capacitor. The circuit produces a current that is a logistic function of the change in voltage on the gate, with an input-referred offset voltage that is a logarithmic function of time. Folding operation for analog-to-digital conversion is obtained by differentially combining currents from a bank of these comparators. A prototype 128-channel parallel 4-bit gray-code analog-to-digital converter has been implemented in a 0.5 μm CMOS process, delivering 128 MS/sec at 76 mW power dissipation.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); integrating circuits; low-power electronics; 0.5 micron; 4 bit; 76 mW; CMOS; MOS correlated double sampling comparator; analog-to-digital conversion; folding circuit; gray-code analog-to-digital converter; input-referred offset voltage; log-domain integrator; logistic function; power dissipation; subthreshold nMOS transistor; Analog-digital conversion; CMOS process; Coupling circuits; Logistics; MOS capacitors; MOSFETs; Power dissipation; Prototypes; Sampling methods; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010663

Filename

1010663