DocumentCode
1812486
Title
Dynamics of high-frequency CMOS dividers
Author
Singh, Ullas ; Green, Michael
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
Volume
5
fYear
2002
fDate
2002
Abstract
Frequency dividers are an essential part of broadband communications IC´s. They are often the most difficult part of a circuit designed to operate at very high frequencies, especially in CMOS. In order to optimize the circuit for high frequency performance, it is necessary to understand the dynamics of the dividers. This paper presents an analysis of the dynamics of high frequency CMOS dividers and sets some guidelines for circuit design.
Keywords
CMOS logic circuits; circuit optimisation; flip-flops; frequency dividers; high-speed integrated circuits; logic design; CML blocks; CMOS frequency dividers; D flip-flop; HF dividers; broadband communications ICs; circuit optimization; design guidelines; dynamics analysis; high-frequency CMOS dividers; positive feedback; Application specific integrated circuits; Broadband communication; CMOS technology; Circuit synthesis; Clocks; Flip-flops; Frequency conversion; Guidelines; VHF circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1010730
Filename
1010730
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