Multi-gates SOI LDMOS for improved on-state performance

SOI LDMOS with multi-gates structure is proposed and fabricated. In this structure, the long gate of the conventional LDMOS (C-LDMOS) is split into four short gates. There is an n+ doped region between two adjacent short gates. The multi-gates structure enhances electric field in the channel region, leading to a higher electron velocity which will induce a larger channel current. The experimental results demonstrate that the proposed four gates LDMOS (FG-LDMOS) shows 4.5% increase in breakdown voltage, 19.2% reduction in on-state resistance and 30.5% improvement in peak transconductance compared with the C-LDMOS.