• DocumentCode
    1813663
  • Title

    Generalized ILP scheduling and allocation for high-level DSP synthesis

  • Author

    Lucke, Lori E. ; Parhi, Keshab K.

  • Author_Institution
    Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
  • fYear
    1993
  • fDate
    9-12 May 1993
  • Abstract
    Integer linear programming (ILP) techniques have recently been proposed to solve the single iteration scheduling problem. In the present work, the integer linear programming formulation is generalized to support unfolded schedules. A new time assignment formulation which automatically pipelines and retimes the dataflow graph (DFG) is presented. A new processor allocation formulation which automatically unfolds the DFG is also presented. It is noted that this is the first time that systematic unfolding is proposed for improving processor utilization on digital signal processing architectures. These models fully optimize the processor utilization for a specific iteration period
  • Keywords
    high level synthesis; dataflow graph; high-level DSP synthesis; integer linear programming formulation; processor allocation formulation; systematic unfolding; time assignment formulation; unfolded schedules; Delay effects; Digital signal processing; Feedback loop; Flow graphs; High level synthesis; Integer linear programming; Iterative algorithms; Processor scheduling; Signal processing; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0826-3
  • Type

    conf

  • DOI
    10.1109/CICC.1993.590480
  • Filename
    590480