Title :
Managing cache partitioning in multicore processors for certifiable, safety-critical avionics software applications
Author_Institution :
Technical Marketing Manager
Abstract :
• With cache partitioning & memory pools • Bound WCET behavior much more tightly with ACET behavior. • Minimize “budgeted-but-unused” time. • Enable much higher levels of processor utilization. • Simplify interference pattern analysis in single-core and multicore environments. • Simplify verification & certification processes.
Conference_Titel :
Digital Avionics Systems Conference (DASC), 2014 IEEE/AIAA 33rd
Conference_Location :
Colorado Springs, CO, USA
Print_ISBN :
978-1-4799-5002-7
DOI :
10.1109/DASC.2014.6979681
