DocumentCode :
1814581
Title :
Reducing wasteful recurrence of aborts and stalls in hardware transactional memory
Author :
Hashimoto, Koji ; Eto, Masamichi ; Horiba, Shoichiro ; Tsumura, Tomoaki ; Matsuo, Hiroshi
Author_Institution :
Nagoya Inst. of Technol., Nagoya, Japan
fYear :
2013
fDate :
1-5 July 2013
Firstpage :
374
Lastpage :
381
Abstract :
Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilities. Hence, transactional memory has been proposed and studied for lock-free synchronization. However, the performance can decline with some conflict patterns in TM. Therefore, this paper proposes two methods to restrain the occurrence of very harmful conflicts. The one relieves starving writers who will keep stalling for a long time. The other serially executes highly conflicted transactions which tend to abort repeatedly. The result of the experiment shows that the merged model of these two methods improves the performance 72.2% in maximum and 28.4% in average.
Keywords :
concurrency control; multi-threading; multiprocessing systems; parallel programming; performance evaluation; synchronisation; transaction processing; hardware transactional memory; lock-based thread synchronization techniques; lock-free synchronization; multicore processors; parallel programming; wasteful abort recurrence reduction; wasteful stall recurrence reduction; Coherence; Hardware; Memory management; Message systems; Scalability; Synchronization; System recovery; Hardware transactional memory; futile stalls; starving writer;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computing and Simulation (HPCS), 2013 International Conference on
Conference_Location :
Helsinki
Print_ISBN :
978-1-4799-0836-3
Type :
conf
DOI :
10.1109/HPCSim.2013.6641443
Filename :
6641443
Link To Document :
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