• DocumentCode
    1815519
  • Title

    A high density datapath layout generation method under path delay constraints

  • Author

    Nakao, Hiroomi ; Kitada, Osamu ; Hayashikoshi, Michiko ; Okazaki, Kaoru ; Tsujihashi, Yoshiki

  • Author_Institution
    Mitsubishi Electric Corp., Hyogo, Japan
  • fYear
    1993
  • fDate
    9-12 May 1993
  • Abstract
    A novel method for producing high-density datapath layouts under path delay constraints is proposed. The authors have adopted an array-compiler for generating layouts of functional blocks, and a place-and-route program for generating an overall layout. For linear placement of functional blocks, they have applied the A-algorithm with a new cost function which has the terms of path delay constraints and track number. This makes it possible to find a placement of functional blocks which leads to a high-density datapath layout that satisfies all path delay constraints. With the proposed method, the authors successfully generated several datapath layouts realizing the desired performance. The density of the layout ranges from 6.1 to 8.5Ktr./mm2, which is sufficiently high
  • Keywords
    circuit layout CAD; A-algorithm; array-compiler; cost function; datapath layout generation method; high density; layouts of functional blocks; linear placement; path delay constraints; place-and-route program; track number; Application specific integrated circuits; Cost function; Delay; Design automation; Large scale integration; Minimization; Rails; Routing; Variable structure systems; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0826-3
  • Type

    conf

  • DOI
    10.1109/CICC.1993.590683
  • Filename
    590683