DocumentCode :
1815685
Title :
A 7 MB/sec (65 MHz), mixed-signal, magnetic recording channel DSP using partial response signaling with maximum likelihood detection
Author :
Philpott, Rick ; Kertis, Robert ; Richetta, Ray ; Schmerbeck, Tim ; Schulte, Don
Author_Institution :
IBM, Rochester, MN, USA
fYear :
1993
fDate :
9-12 May 1993
Abstract :
A mixed-signal, 6.0-MByte/s PRML (partial-response maximum-likelihood) read/write channel has been developed using analog circuits and 20K CMOS gates on a single chip. The 7.5-mm2 chip uses a 5-V, 1-μm, BiCMOS process with a 6-GHz NPN and a 1-GHz PNP and is packaged in a 100 lead metal QFPK. The overall chip architecture is discussed along with specific analog functions and their circuit techniques. This IC will allow production of a 2-GByte, 3.5-in, rigid disk drive with low error rates
Keywords :
hard discs; 1 micron; 2 GByte; 3.5 in; 5 V; 6 MByte/s; 65 MHz; BiCMOS process; CMOS gates; QFPK; analog circuits; chip architecture; magnetic recording channel DSP; maximum likelihood detection; mixed-signal; partial response signaling; read/write channel; rigid disk drive; Analog circuits; BiCMOS integrated circuits; CMOS analog integrated circuits; Digital signal processing; Digital signal processing chips; Disk drives; Lead; Magnetic recording; Packaging; Production;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
Type :
conf
DOI :
10.1109/CICC.1993.590689
Filename :
590689
Link To Document :
بازگشت