A 64-bit adder by pass transistor BiCMOS circuit

Author

Ueda, Kimio ; Suzuki, Hiroaki ; Suda, Kakutaro ; Tsujihashi, Yoshiki ; Shinohara, Hirofumi

Author_Institution

Mitsubishi Electric Corp., Hyogo, Japan

fYear

1993

fDate

9-12 May 1993

Abstract

The authors describe a 64-b carry look ahead (CLA) adder using a novel pass transistor BiCMOS circuit. In this BiCMOS circuit, the outputs of pass transistors are connected directly to the bases of output bipolar transistors. The circuit has a reduced intrinsic delay time, and it shows a speed advantage over CMOS circuits at any load capacitance. A 64-b CLA adder was fabricated using a 0.5-μm BiCMOS process. The BiCMOS circuits are used in full adders, carry path circuits, and carry select circuits in the adder. A critical path delay time of 3.5 ns was obtained at a supply voltage of 3.3 V. This represents a 25% improvement over the adder based on CMOS technology

Keywords

adders; 0.5 micron; 3.3 V; 3.5 ns; 64 bit; ASIC; carry look ahead; carry path circuits; carry select circuits; critical path delay time; full adders; pass transistor BiCMOS circuit; reduced intrinsic delay time; Adders; BiCMOS integrated circuits; Bipolar transistors; CMOS logic circuits; CMOS technology; Capacitance; Delay effects; Inverters; MOSFETs; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0826-3

Type

conf

DOI

10.1109/CICC.1993.590698

Filename

590698