Title :
A square-root domain differentiator
Author :
Vlassis, S. ; Psychalinos, C.
Author_Institution :
Phys. Dept., Aristotle Univ. of Thessaloniki, Greece
Abstract :
In this paper, a square-root domain differentiator circuit is proposed for the first time in the literature. The implementation is based on an appropriate input stage that converts the input current into a compressed voltage at the capacitor´s node and also senses the corresponding capacitor´s current. The overall configuration of the differentiator is also constructed from geometric-mean and multiplier blocks. Simulation results confirm the correct operation of the proposed circuit
Keywords :
analogue processing circuits; current-mode circuits; differentiating circuits; analog signal processing applications; compressed voltage; current-mode squarer; four-quadrant multiplier; geometric-mean blocks; input stage; multiplier blocks; square-root domain differentiator circuit; Circuit simulation; Circuit topology; Dynamic range; Filters; Laboratories; MOS capacitors; MOSFETs; Physics; Psychology; Voltage;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Conference_Location :
Phoenix-Scottsdale, AZ
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010963
