Title :
On testability of checkable digital circuits under pseudorandom signals
Author :
Romankevich, A. ; Groll, V.
Author_Institution :
Kiev Polytech. Inst., Ukraine
Abstract :
Summary form only given. Checkable digital circuits synthesis method and algorithm are proposed. The essence of the method is in the insertion of probability converters into predetermined nodes of the original circuit. The converters are based on XOR-elements, whose one input is connected to the equal probability sequences´ source
Keywords :
circuit testing; design for testability; digital circuits; logic design; logic testing; probability; XOR-elements; algorithm; checkable digital circuits; probability converters; pseudorandom signals; synthesis method; testability; Circuit faults; Circuit testing; Digital circuits; Hardware; Input variables; Redundancy;
Conference_Titel :
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-7039-8
DOI :
10.1109/EDTC.1995.470327
